Digital Waveform Synthesizer User's Guide

This article describes the CSU-CHILL Digital Waveform Synthesizer, used on the CHILL and Pawnee weather radars.

Overview

Timing Block Theory of Operation

The timing block uses a small 1kx32 bit timing memory on the FPGA to control its operations. The memory is dual-ported, and may be written by the host computer, while the internal timing logic uses the memory to control its operation.

The 32 bits of each word from the timing memory is partitioned as follows:

31-24	23	22-21	19-0
Triggers 7-0	Reset	Triggers 10-8	Time stamp

Structure of a single timing control word

Each trigger output has an output flip flop associated with it. The timing logic has a 20-bit time counter, which increments at the rate of 40 MHz. Another counter, the address counter, is used to address the timing memory. The time counter is compared to the current output of the timing memory, when a match is detected, the following actions are taken:

If the reset bit is set, clear the time and address counters to zero, clear all the output flip flops.
If reset bit is clear, use the Trigger[10..0] bits to toggle the output flip flops, and increment the address register by one.

Thus, if the timing memory is filled in with control words whose time stamp is monotonically increasing, then any combination of triggers can be generated, while only using a small amount of memory.

On each 'reset' event, the pulse count is incremented. When the pulse count reaches the specified maximum (either through register 0x85 or 0x98-0x9F), it is reset back to zero. A special case is introduced, where if the pulse count reaches the value specified in register 0x86, then the timing memory read address is moved to 0x200. By storing an alternate set of timing values starting at this address, it becomes easy to implement block-PRF pulsing schemes, using minimum timing memory.

Trigger mapping

The trigger block outputs are mapped to the outputs on the FPGA in the top-level design. This design may be modified to suit the end-use of the board. As of this writing, two top-level designs are available: the stock CHILL design, and a modified design to suit the needs of the NCAR S-Pol radar. The table below shows this mapping. Note that the top-level design may include some glue-logic to further modify the output of the triggers before being delivered to the I/O pins of the FPGA.

Trigger number	Bit	CSU-CHILL output	NCAR/S-Pol output
0	24	DSP Trigger	"RFPLSST"
1	25	Pretrigger H	H/V Flag
2	26	Pretrigger V	$T_{0}-6$
3	27	RF/DUC Trigger H	RF Gate (also triggers DUCs)
4	28	RF/DUC Trigger V	RF Drive
5	29	Test Pulse	Test Pulse
6	30	Receiver trigger, H	Post Charge
7	31	Receiver trigger, V	Modulator Charge
8	20	RF Cover Pulse, H	Mid PRI
9	21	RF Cover Pulse, V	Trigger Charge
10	22	Unassigned	Modulator Discharge

Timing trigger to output mapping

Register Map

This section describes all the registers available on the board that are accessible through the host controller.

Type	Address	Description
Reset	0x10	Reset FPGA
GPIO	0x11	GPIO port
DUC control registers	0x60	DUC Chip version
	0x61	Frequency, Byte 1 (LSB)
	0x62	Frequency, Byte 2
	0x63	Frequency, Byte 3
	0x64	Frequency, Byte 4 (MSB)
	0x65	Phase (LSB)
	0x66	Phase (MSB)
	0x67	Configuration Word 1 (LSB)
	0x68	Configuration Word 2
	0x69	Configuration Word 3 (MSB)
	0x6A	DAC A Offset (LSB)
	0x6B	DAC A Gain (LSB)
	0x6C	DAC A Gain/Offset (MSB)
	0x6D	DAC B Offset (LSB)
	0x6E	DAC B Gain (LSB)
	0x6F	DAC B Gain/Offset (MSB)
Waveform Memory Control	0x80	Waveform Memory Control
	0x81	Waveform Memory Index
	0x82	Waveform Memory Data LSB
	0x83	Waveform Memory Data MSB
	0x84	Waveform Memory Write Bank Select
	0x85	Waveform Memory Integration Cycle size
	0x86	Waveform Memory Breakpoint set
Burst Length Registers	0x90	Bank 0 burst length
	0x91	Bank 1 burst length
	0x92	Bank 2 burst length
	0x93	Bank 3 burst length
	0x94	Bank 4 burst length
	0x95	Bank 5 burst length
	0x96	Bank 6 burst length
	0x97	Bank 7 burst length
Sequence Length Registers	0x98	Bank 0 sequence length
	0x99	Bank 1 sequence length
	0x9A	Bank 2 sequence length
	0x9B	Bank 3 sequence length
	0x9C	Bank 4 sequence length
	0x9D	Bank 5 sequence length
	0x9E	Bank 6 sequence length
	0x9F	Bank 7 sequence length
Timing Block Configuration	0xA0	Timing Configuration Register
	0xA1	Timing Memory Address, Low
	0xA2	Timing Memory Address, High
	0xA3	Timing Memory Data
Command Register	0xF0	Command register

Reset FPGA

Address 0x10. Writing the special value 0xFF to this register causes a board-level reset. All board registers return to their power-on default values.

GPIO

Address 0x11. Any value written to this port appears at the GPIO<7..0> pins of the board.

DUC Control Registers

This group of registers allows the digital upconverters to be programmed.

DUC Chip version

Address 0x60. Returns the current chip version of the DUCs used.

Frequency

Addresses 0x61 - 0x64. This is the 32-bit tuning word used to set the output frequency of the digital upconverters. This is computed by using the following formula:

\mathrm {FTW} ={\frac {f\cdot 2^{32}}{f_{clk}}}

Here, $f$ is the desired frequency, while $f_{clk}$ is the clock frequency of the DUC, which is fixed at 160 MHz.

Phase

Addresses 0x65-0x66. The phase offset of the digital upconverters. Please see the DAC5686 user manual for more information.

Configuration Word

Addresses 0x67-0x69. This word controls the operation of the Digital Upconverter chips.

7	6	5	4	3	2	1	0
Address	0x67			Access	W
Mode		Div		Sel		Counter	Full Bypass
Address	0x68			Access	W
7	6	5	4	3	2	1	0
SSB	INTERL	SINC	DITH	SYNC_PHSTR	NCO	SIF4	TWOS
Address	0x69			Access	W
7	6	5	4	3	2	1	0
DUALCLK	DDSGAIN		RSPECT	QFLAG	PLL Range		REV_BBUS

Please consult the DAC5686 manual and the waveform generator schematic before attempting to reprogram these registers away from their default.

The remaining DAC registers are not used by the particular configuration present on the CHILL waveform generator board.

Waveform Memory Control

This set of registers controls the operation of the data source for the digital upconverters. This data source reads the on-board SRAM, and passes the data to the upconverters.

Control register

This is the control register for the digital waveform memory.

7	6	5	4	3	2	1	0
Address	0x80			Access	W
Trigger Enable	reserved			Burst Increment	Bank Number

Memory Control Register

Trigger Enable: Allows the memory controller to perform SRAM fetch commands and pass the data to the digital upconverters.
Burst Increment: When set, permits the burst number to increment. This is used when implementing a waveform with inter-pulse phase coding, where successive bursts are used to store the original waveform with a phase shift applied.
Bank Number: Stores the current memory bank which is read to obtain data for the digital upconverters. If a waveform spans multiple banks, issuing a bank switch will cause the new waveform to be generated after the current burst has completed.

Waveform memory index

Address: 0x81. This register controls the sample index to which subsequent host writes will take place.

Waveform memory data, LSB

Address: 0x82. This register stores the LSB to be written to the waveform memory. Note that writing to this register does not trigger a write cycle, the MSB needs to be written to trigger a write.

Waveform memory data, MSB

Address: 0x83. This register stores the MSB to be written to waveform memory. It is assumed that the LSB has already been written to register 0x82.

Waveform memory write bank select

Address: 0x84. Controls which bank writes are made to. Only the lowest three bits are used for bank selection, the remaining bits are reserved.

Waveform Memory Integration Cycle size

Address: 0x85. When not in inter-pulse phase shifting mode, this register controls the length of the integration cycle. When using phase shifting mode, the integration cycle length is derived from the sequence length.

Waveform Memory Breakpoint set

Address: 0x86. When the current pulse count reaches this value, the timing memory index is immediately shifted to address 0x200. This permits easy implementation of block-PRF schemes.

Burst Length Registers

Addresses: 0x90-0x97. These registers control the length of each burst of samples. There is one separate register per bank.

Sequence Length Registers

Addresses: 0x98-0x9F. These registers control the number of sample bursts per sequence. There is one separate register per bank.

Timing Block Configuration

These registers configure the timing generator block on the board.

Control Register

7	6	5	4	3	2	1	0
Address	0xA0			Access	R/W
Reserved		Trigger Enable	Timing Reset	Triggered	Armed	Mode

Timing Control/Status Register

Trigger Enable: Enables generation of timing triggers
Timing Reset: Causes the timing block to be reset. This does not clear the timing memory. Exact action depends on the mode
Triggered: Set high by the board when a valid trigger has been received on the external trigger input
Armed: Set high by the board when waiting for a valid trigger on the external trigger input
Mode: Controls the timing mode.

Mode	Description
00	Normal mode. On reset, the FPGA re-syncs the DUCs, then generates triggers.
01	Triggered mode. On reset, the FPGA waits for a rising edge on the external trigger input. When this occurs, the DUCs are re-synced and the trigger generation proceeds.
10	Single-shot mode. On reset, the FPGA waits for a rising edge on the external trigger input. When this occurs, the DUCs are re-synced and one cycle of triggers is produced. After the cycle is done, the FPGA waits again for another trigger.

Trigger operating modes

Address Registers

Address: 0xA1-0xA2. These registers, when written, set the address that the next write to the data timing data register will write. 0xA1 is the LSB, 0xA2 is the MSB.

Data Register

Address: 0xA3. Writing to this register causes a write to the timing control memory. It also will automatically increment the address register to point to the next address. Note that the address mapping is big-endian, as shown in the table below:

Timing Word Index	Bytes
0	3	2	1	0
1	7	6	5	4
...
1023	4095	4094	4093	4092

Timing table address mapping

Command Register

This register, at address 0xF0, is not an actual register, but writing various command bytes will alter the behavior of the board. The table below is a list of all supported commands.

Command	Description
0x55	Reset FPGA
0xF0	Single-tone mode. Issue this command to cause the digital upconverter to enter a mode where the output is a CW signal (no modulation).
0xF1	DUC Mode. Issue this command to cause the digital upconverter to enter modulated output mode (default).
0xF2	Set User LED.
0xF3	Clear User LED.
0xF4	Set transfer switch toggle enable bit.
0xF5	Clear transfer switch toggle enable bit.
0xF6	Set inter-pulse phase modulation mode.
0xF7	Clear inter-pulse phase modulation mode.
0xF8	Set transmit enable bit
0xF9	Clear transmit enable bit
0xFA	Set the calibration mode enable
0xFB	Clear the calibration mode enable

Command list